1. Field of the Invention
The present invention relates to an improved method of manufacturing a semiconductor device, more particularly to an improved method including a chemical-mechanical polishing step for planarizing a dielectric film.
2. Description of the Related Art
Semiconductor devices are commonly manufactured by processing a semiconductor wafer to simultaneously form a plurality of devices, each of which may be referred to as a die or a chip. The processing steps include the formation of dielectric films, typically oxide films, for various purposes, such as filling in trenches in the wafer, or insulating layers of metal wiring.
When a dielectric film is formed, it may have an uneven surface topography, mimicking the underlying pattern of trenches or wires. To provide a sufficiently flat surface on which to form the next layer, it is often necessary to planarize the dielectric film by chemical-mechanical polishing (CMP). When conventional methods are used, the planarization performance is known to depend strongly on the density of the underlying trench or wiring pattern.
FIG. 1 shows an example of a semiconductor wafer on which a plurality of chips 2 are being formed. The chips 2 are surrounded by a peripheral area 4 which is featureless except for a marking 6, written by a laser beam, used for identification of the wafer lot. The area occupied by the chips 2 will be referred to as the effective device area 8. The effective device area 8 is separated from the peripheral area 4 by grid lines 10 approximately one hundred micrometers (100 xcexcm) wide, as shown in FIGS. 2 and 3.
FIG. 2 illustrates the wafer after deposition of an inter-layer dielectric film 12: either an inter-metal dielectric (IMD) film or a pre-metal dielectric (PMD) film. The substrate 13 shown in FIG. 2 may be either another dielectric film or the semiconductor (e.g., silicon) wafer substrate. Even if this substrate 13 has a perfectly flat surface, the topography of the IMD or PMD film 12 includes vertical steps of approximately the same height as those in the wiring layer 14 formed on the substrate 13. The average thickness of the dielectric film 12 is greatest in the peripheral area 4, where the pattern density of the wiring layer 14 approaches one hundred percent (100%), and is least in the highly patterned effective device area 8.
FIG. 3 illustrates the wafer at an earlier processing stage, after deposition of a shallow trench isolation (STI) dielectric (oxide) film 16. The topography of the STI film 16 includes vertical steps of approximately the same height as the trench depth, this depth being measured from the top of a nitride film 18, which is used as a mask when the trenches are etched in the semiconductor substrate 19, to the bottoms of the etched trenches 20. Once again, the average thickness of the dielectric film 16 is greatest in the peripheral area 8 and least in the effective device area 4.
FIGS. 4 to 7 illustrate the chemical-mechanical polishing of the IMD or PMD film 12 in FIG. 2. FIG. 4, which is identical to FIG. 2, shows the starting state. In FIG. 5, a slurry 21 is dripped onto the dielectric film 12, an elastic polishing pad 22 is pressed against the oxide film 12, and the dielectric film 12 is polished with a rotary motion. The polishing pad 22 is deformed by the topography of the dielectric film 12, giving rise to local variations in polishing pressure. Higher parts of the dielectric film 12 are polished faster than lower parts, so the polishing process smoothes out the topography of the dielectric film 12, as shown in FIG. 6. Despite this, the average thickness of the material to be removed in the peripheral area 4 is so much greater than the average thickness in the effective device area 8 that at the end of the polishing process, the surface of the dielectric film 12 remains higher in the peripheral area 4 than in the effective device area 8, as shown in FIG. 7.
The polishing process is controlled to reduce the dielectric film 12 to a predetermined thickness in the effective device area 8. The thickness of the dielectric film 12 in the peripheral area 4 is not of direct concern, since no devices are formed in this area, but this thickness influences the final thickness achieved in the adjacent grid-line area 10 and in nearby parts of the effective device area 8. Because of its high average thickness, the peripheral area 4 absorbs a disproportionate share of the polishing pressure near the circumference of the wafer, thereby reducing the polishing rate in the outer parts of the effective device area 8. Consequently, as can be seen in FIG. 7, the polished surface of the effective device area 8 is far from flat. Resulting problems include defocusing in subsequent lithography steps and incomplete etching in subsequent etching steps, leading to poor device yields.
One approach to solving these problems is more aggressive polishing, to reduce all areas of the wafer to the same height. Such aggressive polishing, however, risks exposure of the wiring pattern in chips near the center of the wafer.
Another approach is to surround the effective device area 8 with dummy devices, thereby eliminating the non-patterned peripheral area. FIG. 8 shows an example of a semiconductor wafer in which the effective device area 8 is surrounded by dummy devices or dummy chips 24, except where the marking 6 is formed. The effective device area 8 is separated from the dummy chips 24 by grid lines 10 approximately 100 xcexcm wide, as shown in FIGS. 9 and 10. The dummy chips 24 are patterned with substantially the same pattern density as the effective device area 8.
FIG. 9 shows an IMD or PMD film 26 covering a wiring pattern 27 formed on a substrate 28 (either an underlying dielectric film or the semiconductor wafer substrate). FIG. 10 shows an STI dielectric (oxide) film 30 formed on a nitride film 32 on a silicon wafer substrate 34. In both cases, since the pattern density is the same in the dummy chips 24 as in the effective device area 8, the average thickness of the dielectric film is substantially the same in these two areas 8, 24.
FIGS. 11 to 14 illustrate the chemical-mechanical polishing of the IMD or PMD film 26 in FIG. 9. FIG. 11 shows the state before polishing begins; the topography of the IMD or PMD film 26 mimics the wiring pattern 27 below. FIG. 12 illustrates the start of the polishing process, showing the polishing pad 22 and slurry 21. FIG. 13 illustrates a later stage in the polishing process, showing that the dummy chips 24 are polished at substantially the same rate as the effective device area 8. FIG. 14 illustrates the end of the polishing process. The dummy chips 24 have substantially no effect on the final thickness of the dielectric film 26 in the effective device area 8, and a satisfactory degree of planarity is achieved.
Semiconductor wafers with dummy chips are now in general use for the manufacture of semiconductor devices on fabrication lines in which chemical-mechanical polishing is employed. Dummy chips do not completely eliminate uneven planarization, however, and they introduce a serious new problem.
The reason why dummy chips do not completely eliminate uneven planarization is that no dummy chips are formed in the wafer area where the marking 6 is written. The visibility of the marking would be impaired if it were to be overwritten on a patterned dummy-chip area. Accordingly, planarization irregularities tend to persist in chips located near the marking.
The new problem introduced by the dummy chips is that much additional processing is needed to pattern them. This is particularly true in lithography steps carried out with exposure apparatus of the step-and-repeat type (e.g., with a stepper apparatus). Since the dummy chips will not become products, the time spent processing them reduces the productivity of the manufacturing process, and increases the cost of ownership (CoO) of the processing equipment, including personnel costs. Since the dummy chips are numerous, and since they have to be patterned anew before each chemical-mechanical polishing step in the fabrication process, the impact on productivity and cost is considerable, and the capability of the fabrication line for high-volume production is impaired.
An object of the present invention is to provide an improved method of manufacturing a semiconductor device, such that when the device is planarized by chemical-mechanical polishing, good planarity is obtained without significant negative impact on cost and productivity.
The invented method of manufacturing a semiconductor device includes the steps of:
(a) forming a dielectric film covering a substrate having an effective device area surrounded by a peripheral area;
(b) forming a resist mask, preferably by a single lithography exposure, covering the dielectric film in the effective device area and leaving at least part of the dielectric film exposed in the peripheral area;
(c) etching the exposed part of the dielectric film, preferably by wet etching;
(d) removing the resist mask; and
(e) planarizing the dielectric film by chemical-mechanical polishing.
The resist mask formed in step (b) may expose all of the dielectric film beyond a certain distance from the effective device area, or may be patterned to expose only part of the dielectric film beyond this distance.
The invented method yields good planarity by removing high parts of the dielectric film from the peripheral area, so that these parts do not reduce the polishing pressure in the effective device area.
Impact on process cost and productivity is slight, because the resist mask formed in step (b) does not have to be accurately patterned or aligned, and the etching process in step (c) does not have to be tightly controlled.